Programmes with clear status
Programmes under active engineering or research. Labels say what stage each item is in. Nothing here is a shipping silicon product.
Status labels: Research, Prototype, In Development, Partnership Program, Design Service. First silicon is not targeted before 2029.
- Trust boundary
- Supporting logic
- Signed data in flight
Current programmes
Pre-silicon. Architecture specified; RTL in progress; FPGA next. Figures are design targets, not measured silicon results.
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In Development
Trusted Compute Platform
Four-layer architecture for attributable edge inference and infrastructure compute. Architecture defined; RTL in progress.
Open programme -
In Development
TrustCore
Hardware root of trust: per-die identity, measured boot and result signing. RTL work is underway.
Open programme -
Research
InferEdge
Joule-bounded edge inference accelerator. Architecture class defined; not a shipping part.
Open programme -
Research
SecureGrid
Infrastructure SoC for metering and grid-edge hosts. Architecture defined; FPGA path next.
Open programme -
Research
Attested Infrastructure Inference
Fleet verification model that admits only proof-carrying results. Design intent, not a deployed product.
Open programme -
Prototype
FPGA Validation Path
Board-level validation of architecture blocks before any tape-out commitment.
Open programme -
Partnership Program
University Partnership Programme
Curriculum, internships and supervised research with engineering faculties in Africa.
Open programme -
Design Service
Semiconductor Design Services
Commercial architecture, RTL, FPGA, verification and embedded engagements available now.
Open programme
Publications and the research hub
Programme status lives on this page. Published papers and collaboration routes sit under Resources → Research. The Attested Infrastructure Inference whitepaper is the current public reference document.
Engage on a programme
Partner on research, design services or university collaboration. Status labels stay honest.