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Implementation

ASIC Development

A flow whose last step cannot be undone

Close each question in the stage that can still answer it. Nelix has not taped out, silicon is targeted no earlier than ~2029.

Architecture defined Pre-silicon
Status
Architecture defined
Validation gate
FPGA bring-up before RTL freeze
Timing closure
STA across PVT corners
De-risking
MPW shuttle for a first part
Tape-out
Not performed; not before ~2029

Design targets · not measured silicon results

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Trust domain Trusted compute
Nelix trusted compute domain Floorplan with four nested planes: board domain, package, die, and a central trust island for device identity, measurement and signing. Compute, memory, sensor I/O, metrology, crypto and telemetry route into a ring bus. Only signed data leaves through an attestation export port. Board domain Package Die Die extent Package extent Compute Bounded array Memory Measured store I/O phy Sensor ingress Metrology Sense & sample Crypto Sign & seal Telemetry Signed export Ring bus Trust island Root of trust Key slots Identity · measure · sign Port signed Attestation export Nothing else crosses
  • Trust boundary
  • Supporting logic
  • Signed data in flight
ASIC Development · labelled architecture
Infrastructure equipment in the field conditions this mechanism is designed for
Field condition the mechanism is specified against
PROBLEM

Tape-out is where mistakes stop being editable

After masks are ordered, a bug costs a respin. Timing, DFT and physical sign-off each catch failures that more simulation will not.

While running Runtime verification
Continuous runtime verification A conceptual die floorplan for continuous measurement. An always-on measurement engine occupies the left of the die, with a four-phase cycle beneath it: sample, hash, extend, compare. To its right a recessive band shows workload activity in three lanes of uneven task footprints. A sample bus runs under the band and a comb of taps drops from it into a digest chain of linked cells, one per epoch, which the light extends from left to right. One epoch is flagged and re-measured. Beneath the chain the measured history stacks downward in rows that fade as they age, and the chain has no entry from its left end, so the record can only be extended and never rewound. Fresh evidence leaves through a port on the right edge. Operating die · power on Measure engine Always on Sampler Hash macro Every epoch not only at boot Sample Hash Extend Compare Workload activity L0 L1 L2 Sample bus Rolling digest E0 E1 E2 E3 E4 E5 E6 No rewind Re-measure Measured history E6 E5 E4 E3 Fresh quote Measurement continues for as long as the device runs
  • Measured epoch
  • Flagged for re-measure
  • Light = the digest being extended
Boot-time proof goes stale, so measurement continues while the device works and the evidence an operator asks for is always current.
Gate commitment on closed questions · design intent
APPROACH

Gate commitment on closed questions

FPGA validation before RTL freeze; constraint-driven synthesis; STA across PVT; DFT early; physical re-closure on parasitics; sign-off before any mask set. MPW shuttle for first silicon.

ORDER OF OPERATIONS

Sequence

Order is the mechanism, and nothing here is optional.

Sequence ASIC Development
The enforced order of operations, 6 steps from first to last Sequence diagram with a trunk on the left edge. Steps in order: Micro-architecture; RTL + verify; Synthesis; Test insertion; Physical; Sign-off. Gate ticks sit between steps; the last step is the only exit. Enforced order 01 Micro-architecture Structure and budgets fixed before synthesis RTL 02 RTL + verify Implemented against coverage goals 03 Synthesis Mapped under explicit timing constraints 04 Test insertion Scan and memory BIST added 05 Physical Floorplan, grid, clocks, route; re-close on parasitics 06 Sign-off All checks pass before tape-out is considered No step may be skipped The enforced order of operations, 6 steps from first to last Sequence diagram with a trunk on the left edge. Steps in order: Micro-architecture; RTL + verify; Synthesis; Test insertion; Physical; Sign-off. Gate ticks sit between steps; the last step is the only exit. 01 Micro-architecture Structure and budgets fixed before synthesis RTL 02 RTL + verify Implemented against coverage goals 03 Synthesis Mapped under explicit timing constraints 04 Test insertion Scan and memory BIST added 05 Physical Floorplan, grid, clocks, route; re-close on parasitics 06 Sign-off All checks pass before tape-out is considered
  • Ordered step
  • Only exit
Each step taps the trunk once; the gates between them are why the order holds.
Wafer probe station
Wafer probe station
PROPERTIES

What follows from the diagram

  1. FPGA before freeze

    Architecture questions closed on a reprogrammable platform

  2. STA across corners

    Setup and hold closed over PVT, not a nominal point

  3. DFT early

    Scan and memory BIST so die can be screened

  4. Sign-off gate

    Timing, PI, DRC/LVS before commitment

Engage

Reviewing this mechanism?

The specification can still change. That stops being true after tape-out.

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