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Implementation

FPGA Development

Validate before committing a mask set

Running real RTL against real firmware on FPGA finds awkward boundary behaviour while it is still cheap to fix. FPGA validation is the next milestone and is not complete.

RTL in progress Pre-silicon
Status
RTL in progress
Purpose
Architecture validation before ASIC
Transfers
Function, protocol, firmware integration
Does not transfer
Timing, area, absolute power
Milestone
FPGA validation not yet complete

Design targets · not measured silicon results

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Trust domain Trusted compute
Nelix trusted compute domain Floorplan with four nested planes: board domain, package, die, and a central trust island for device identity, measurement and signing. Compute, memory, sensor I/O, metrology, crypto and telemetry route into a ring bus. Only signed data leaves through an attestation export port. Board domain Package Die Die extent Package extent Compute Bounded array Memory Measured store I/O phy Sensor ingress Metrology Sense & sample Crypto Sign & seal Telemetry Signed export Ring bus Trust island Root of trust Key slots Identity · measure · sign Port signed Attestation export Nothing else crosses
  • Trust boundary
  • Supporting logic
  • Signed data in flight
FPGA Development · labelled architecture
Infrastructure equipment in the field conditions this mechanism is designed for
Field condition the mechanism is specified against
PROBLEM

Simulation covers what the testbench thought to ask

Boundary cases, sagging supply, restore under changed contracts, mesh events during signing, are where the design matters. Finding them after tape-out is not patchable.

While running Runtime verification
Continuous runtime verification A conceptual die floorplan for continuous measurement. An always-on measurement engine occupies the left of the die, with a four-phase cycle beneath it: sample, hash, extend, compare. To its right a recessive band shows workload activity in three lanes of uneven task footprints. A sample bus runs under the band and a comb of taps drops from it into a digest chain of linked cells, one per epoch, which the light extends from left to right. One epoch is flagged and re-measured. Beneath the chain the measured history stacks downward in rows that fade as they age, and the chain has no entry from its left end, so the record can only be extended and never rewound. Fresh evidence leaves through a port on the right edge. Operating die · power on Measure engine Always on Sampler Hash macro Every epoch not only at boot Sample Hash Extend Compare Workload activity L0 L1 L2 Sample bus Rolling digest E0 E1 E2 E3 E4 E5 E6 No rewind Re-measure Measured history E6 E5 E4 E3 Fresh quote Measurement continues for as long as the device runs
  • Measured epoch
  • Flagged for re-measure
  • Light = the digest being extended
Boot-time proof goes stale, so measurement continues while the device works and the evidence an operator asks for is always current.
Real design, real firmware, at speed · design intent
APPROACH

Real design, real firmware, at speed

RTL is synthesised for FPGA and brought up with production firmware. Function and protocol transfer to ASIC; timing, area and absolute power do not.

ORDER OF OPERATIONS

Sequence

Order is the mechanism, and nothing here is optional.

Sequence FPGA Development
The enforced order of operations, 6 steps from first to last Sequence diagram with a trunk on the left edge. Steps in order: Port; Bring-up; Integrate; Instrument; Characterise; Feed back. Gate ticks sit between steps; the last step is the only exit. Enforced order 01 Port RTL adapted to the target fabric 02 Bring-up Clocks, reset and interfaces proven first 03 Integrate Production firmware runs against the design 04 Instrument Trace exposes rare boundary cases 05 Characterise Behaviour and relative energy ranked across variants 06 Feed back Findings return before ASIC commitment No step may be skipped The enforced order of operations, 6 steps from first to last Sequence diagram with a trunk on the left edge. Steps in order: Port; Bring-up; Integrate; Instrument; Characterise; Feed back. Gate ticks sit between steps; the last step is the only exit. 01 Port RTL adapted to the target fabric 02 Bring-up Clocks, reset and interfaces proven first 03 Integrate Production firmware runs against the design 04 Instrument Trace exposes rare boundary cases 05 Characterise Behaviour and relative energy ranked across variants 06 Feed back Findings return before ASIC commitment
  • Ordered step
  • Only exit
Each step taps the trunk once; the gates between them are why the order holds.
Wafer probe station
Wafer probe station
PROPERTIES

What follows from the diagram

  1. Fabric synthesis

    Portability checked by mapping to FPGA resources

  2. Firmware bring-up

    Integration faults appear against real software

  3. Relative energy ranking

    Compare variants; do not predict silicon watts

  4. Explicit limits

    No ASIC claim is built on an FPGA absolute

Engage

Reviewing this mechanism?

The specification can still change. That stops being true after tape-out.

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