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PROGRAMME

Engineering milestones, not launches

No tape-out yet. Milestones below are engineering targets; dates depend on funding and partner availability.

RTL in progress No tape-out
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Talent development pipeline

  1. University

    Cohort intake and coursework

    Active

  2. Mentorship

    Paired design review

    Active

  3. FPGA

    Prototyping and bring-up

    Active

  4. Verification

    Testbench and coverage closure

    Planned

  5. Product

    Tape-out readiness

    Planned

Engineers train on live design work, supervised by the engineers doing it.

Implementation path · target silicon around 2029
STATUS

Five phases, one of them complete

Dates beyond the current phase depend on funding and partners.

  1. Phase 01

    Complete

    Architecture definition

    Platform decomposition, completion state machine, energy contract, and trust continuum specified in the public whitepaper.

    • Platform architecture
    • ICSM specification
    • Energy contract model
    • Threat model

  2. Phase 02

    In progress

    RTL development

    Synthesisable RTL for root of trust and inference datapath, with verification benches alongside.

    • TrustCore RTL
    • InferEdge datapath RTL
    • Verification environment
    • Coverage plan

  3. Phase 03

    Next milestone

    FPGA validation

    Programmable bring-up to validate architecture, energy behaviour, and end-to-end attestation.

    • FPGA prototype
    • Attestation path bring-up
    • Energy characterisation
    • Reference firmware

  4. Phase 04

    Target: post-validation

    Pilot deployment

    Field trials with utility and industrial partners on the FPGA platform before silicon commitment.

    • Partner pilots
    • Field data collection
    • Specification revision

  5. Phase 05

    Target: around 2029

    ASIC implementation

    Physical design and tape-out subject to funding, foundry engagement, and validated demand. No silicon exists today.

    • Foundry selection
    • Physical design
    • Tape-out
    • Characterisation
Illustrative wafer probe station
Wafer probe station
BOUNDARIES

What this does not claim

  • No Nelix silicon exists. Nothing has been fabricated or characterised.
  • No product is available for purchase, sampling or evaluation.
  • Performance and power figures are design targets.
  • Dates beyond the current phase depend on funding and partners.
  • Design services and training are the revenue activity today.

Follow the programme

Partners who engage before FPGA validation influence what gets built.

Partner with Nelix Read the technology