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Edge AI

Inference that completes on the device and proves what produced it

Architecture specified · RTL in progress · no Nelix silicon yet

edge ai context

Decisions taken where there is no link to defer to
Decisions taken where there is no link to defer to
THE CHALLENGE

Local inference solves latency and creates an evidence problem

There are sound reasons to run a model at the device. A camera on a production line cannot wait for a round trip, a clinic may not send patient images off site, and a remote installation has no link to send them over in the first place. What the move gives up is the assurance that came with a controlled environment: nobody downstream can see which model ran, on which firmware, or whether it ran to completion.

Energy is the other half of the problem. Battery and solar powered products have a joule budget per decision, and an accelerator that draws whatever the workload demands will either throttle unpredictably or shorten the deployment. Models are then updated over the air for years after installation, and a fleet that cannot establish which version is resident cannot distinguish a legitimate update from a substituted one.

LIMITATIONS

Why current compute does not serve it

The constraints are structural: placement, power, connectivity and service life, not missing features on a datasheet.

  1. A result carries no provenance

    Edge inference frameworks return a tensor. Nothing in the output identifies the weights, the firmware or the device, so a downstream system has to trust the transport instead of the result.

  2. Accelerators are rated for throughput, not per decision

    Published peak operations per second and operations per watt describe sustained load in a thermal test fixture, which tells a designer little about the joules one completed inference will cost.

  3. Model substitution is not detectable in the field

    Where a model artefact is checked only once at load time, a device altered afterwards keeps returning plausible results from a model the operator never approved.

  4. Interrupted inference fails silently

    On power loss the request simply disappears. The application sees a timeout and cannot tell a refused request from a lost one, or either from a hung device.

  5. Privacy gains cost the operator visibility

    Keeping data on the device also keeps the evidence there, so an operator who stops receiving inputs usually stops being able to check anything at all.

Memory-block silicon
Memory-block silicon
APPROACH

A completion transaction with proof attached

InferEdge is specified around the Inference Completion State Machine. Each request is admitted with an energy contract fixing joule budget, model tier, clock profile and checkpoint policy, then occupies an explicit state from attested input through execution and checkpoint to completion and proof export, or to a stated abort with a reason the application can act on.

TrustCore measures firmware and the model artefact before execution and signs afterwards, so output leaves the device as a result plus an attestation bundle binding the result digest to per-die identity, firmware measurement and model version. The operator verifies that bundle against approved configuration before admitting the result to a workflow, which turns a substituted model into a rejected result rather than an undetected one.

The INT8 and INT4 datapaths and the sub-15 W envelope are design targets in an architecture that has not been fabricated. RTL is in progress, and FPGA validation, where these figures will first be characterised, is the next milestone.

Specified, not measured. RTL in progress; FPGA next; no Nelix silicon yet.

Bounded execution Inference
Bounded, energy-contracted edge inference A conceptual die floorplan for edge inference. Sensor data enters through an ingress block and a quantiser, then runs on a bounded array of compute tiles on a deterministic schedule. A completion state machine, drawn as a ring, admits work, runs it, holds it inside a bound and reports completion; results and a signed proof leave through separate export blocks. Beneath the datapath an energy contract rail fills to a hard stop bar and no further, with the remaining track drawn as an unused ghost. Edge inference domain Ingress Sensor Quantise INT8 / INT4 Npu tiles Bounded array Deterministic schedule Completion state machine Admit Run Bound Done Export Result Proof Signed Both or neither Energy contract Hard bound Never entered Admitted only if it fits One bounded execution
  • Inside the contract
  • Beyond the bound
  • Light stops at the bar
Inference at the edge is a contract: admitted only if it fits the energy budget, and it either completes with a proof or not at all.
Inference completion path · design intent
POSITION

Where Nelix sits in this system

Each request occupies an explicit state from attested input through execution to completion and proof export, or to a stated abort.

A result and its evidence leave together
A result and its evidence leave together
PATHWAY

From energy contract to a result a workflow can admit

Contract, execute, prove and admit — inference as a completion transaction with evidence attached.

  1. Contract

    Agree joule budget, model tier and checkpoint policy

  2. Execute

    Run through explicit completion states, or abort with a reason

  3. Prove

    Export a result digest with device, firmware and model evidence

  4. Admit

    Let the operator verify before anything acts on the result

CAPABILITIES

The mechanisms that address them

Technical mechanisms in the specification. None of these figures have been characterised in silicon.

  1. Energy contract per request

    Joule budget, model tier, clock profile and checkpoint policy are agreed before execution, so a device does not begin a decision it cannot finish.

  2. Explicit abort with a reason

    A request that cannot complete within its contract returns a stated failure and a cause, instead of a timeout the application has to interpret.

  3. Checkpoint and validated restore

    Restore checks checkpoint integrity and contract compatibility before resuming, so recovery after power loss cannot quietly change execution semantics.

  4. Model measured before it loads

    Model artefacts are verified against signed manifests and their measurement is carried into the result, so the version becomes part of the output rather than a deployment record.

  5. Attestation without connectivity

    Bundles are produced and signed locally and can be queued, so verification does not require a live link at the moment of inference.

  6. Fleet-level configuration policy

    Approved firmware and model combinations are expressed once and enforced on ingest for every device reporting into the workflow.

OUTCOMES

What changes if the architecture delivers

Operational consequences stated as design intent, not as measured field results.

  1. Results a workflow can admit on evidence

    Verification happens before a result reaches an automated decision, rather than during the investigation that follows a bad one.

  2. Predictable energy per decision

    Contracted joule budgets let a designer size a battery and panel against decisions per day instead of against a peak power number.

  3. Privacy without losing oversight

    Data can stay on the device while the operator still receives evidence about the firmware and model that processed it.

  4. Field-verifiable model updates

    Because the resident version is measured and reported, a fleet operator can establish what is actually deployed rather than what was dispatched.

PRODUCTS

Platform layers involved

The product family this sector is specified against. Each page states programme stage honestly.

What we need from this sector now

Partnership

The useful conversation now is about workloads and constraints: which models, what energy budget per decision, and what a verifier needs to see. That input is what shapes the RTL.

Partner with Nelix Contact the team
  • Representative models and accuracy requirements from real deployments
  • Energy and duty-cycle constraints from battery and solar powered products
  • Review of the attestation bundle format by the teams that would verify it
  • FPGA-based evaluation with integrators ahead of silicon
SOLUTIONS

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