Long-term platform work driven by the research gap. Production silicon is not shipping.
Named product lines under the AI-accelerators umbrella. Each page carries an honest stage label.
Trust, attestation and power-resilience IP that the platforms are built on.
Evaluation paths and documentation for architecture validation before any tape-out.
Metering, grid-edge hosts and utility operations under intermittent power and connectivity.
Control, gateways and remote monitoring for infrastructure that cannot assume a reliable cloud path.
Trusted compute and identity for sovereign and public-sector programmes. Design intent, not deployed claims.
Additional sector pages for telecom, edge AI and secure embedded contexts.
Hardware-rooted identity, measured boot and attestation topics. Status labelled on each page.
Power interruption and local inference as architectural inputs, not exception handlers.
FPGA and ASIC pathways plus research programmes with clear stage labels.
Architecture through RTL, FPGA and SoC integration — commercial delivery today.
Verification closure, security architecture and embedded bring-up under milestone reviews.
How to engage Nelix on a scoped design programme.
Proposed institutional collaboration — not a claim of signed agreements.
Training and research routes that feed Africa's semiconductor talent pipeline.
Supervised placements and the talent-to-employment path.
Categories only. Logos appear only with verified written permission.
Hubs publish only real documents and posts. Empty hubs say so.
Programme updates and developer paths when content lands.
Accra-based fabless design house. Pre-silicon programme stage stays explicit.
Published roles when listed. General applications stay open.
Select a role to read the detail.
Apply against these engineering areas — openings when published above. CV required; position and availability help us route it.
No specific role selected — general application.
Earlier-career paths run through the talent programme.
