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Architecture class

Attested Infrastructure Inference

Verifiable completed inference under energy constraint

Architecture class for workloads where the operator needs cryptographic evidence of how a result was produced, under energy and connectivity constraints datacentre accelerators ignore.

Architecture defined Pre-silicon
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Wafer probe station

Wafer probe station

Boundary Attestation
Attestation boundary between device and operator A conceptual diagram of the attestation boundary. On the left, inside the device domain, a measurement store, a nonce buffer and a key handle feed a quote generator that binds measurements to a fresh challenge and signs the result. A hatched membrane with a single aperture separates the device from the operator domain on the right, where a verifier checks the quote against a trust anchor and a policy store before issuing an admit or deny decision. Only the challenge and the signed quote pass through the aperture. Device domain Operator domain Attestation boundary One aperture · signed payloads only Measurements Digest chain Nonce Freshness Key handle Attest key Quote Bind & sign Digests Nonce Device id Signed per challenge Verifier Check chain Anchor Root cert Policy Admit rules Decision Admit / deny Signed quote Challenge nonce Inside Outside
  • Signed quote outward
  • Challenge inward
  • Everything else stops at the band
The operator never reaches inside the device: it sends a challenge and checks the signature that comes back.
Attested Infrastructure Inference · architecture, design intent
ARCHITECTURE

Read the architecture

Each state is entered explicitly, failure is a defined transition rather than an absence, and what is drawn is specified rather than measured.

Sequence Attested Infrastructure Inference
The enforced order of operations, 4 steps from first to last Sequence diagram with a trunk on the left edge. Steps in order: Constrained site; Bounded execution; Attestation bundle; Operator verification. Gate ticks sit between steps; the last step is the only exit. Enforced order 01 Constrained site Intermittent power, narrowband, physical access risk 02 Bounded execution Admitted against budget; complete or abort explicitly 03 Attestation bundle Digest bound to identity, firmware, model 04 Operator verification Checked against approved config before use No step may be skipped The enforced order of operations, 4 steps from first to last Sequence diagram with a trunk on the left edge. Steps in order: Constrained site; Bounded execution; Attestation bundle; Operator verification. Gate ticks sit between steps; the last step is the only exit. 01 Constrained site Intermittent power, narrowband, physical access risk 02 Bounded execution Admitted against budget; complete or abort explicitly 03 Attestation bundle Digest bound to identity, firmware, model 04 Operator verification Checked against approved config before use
  • Ordered step
  • Only exit
Every state is entered explicitly, and the gates between them are why the order holds.
While running Runtime verification
Continuous runtime verification A conceptual die floorplan for continuous measurement. An always-on measurement engine occupies the left of the die, with a four-phase cycle beneath it: sample, hash, extend, compare. To its right a recessive band shows workload activity in three lanes of uneven task footprints. A sample bus runs under the band and a comb of taps drops from it into a digest chain of linked cells, one per epoch, which the light extends from left to right. One epoch is flagged and re-measured. Beneath the chain the measured history stacks downward in rows that fade as they age, and the chain has no entry from its left end, so the record can only be extended and never rewound. Fresh evidence leaves through a port on the right edge. Operating die · power on Measure engine Always on Sampler Hash macro Every epoch not only at boot Sample Hash Extend Compare Workload activity L0 L1 L2 Sample bus Rolling digest E0 E1 E2 E3 E4 E5 E6 No rewind Re-measure Measured history E6 E5 E4 E3 Fresh quote Measurement continues for as long as the device runs
  • Measured epoch
  • Flagged for re-measure
  • Light = the digest being extended
Boot-time proof goes stale, so measurement continues while the device works and the evidence an operator asks for is always current.
Mechanism context · design intent
MECHANISMS

What holds, and why

  1. Proof before action

    Control and billing can require provenance, not network trust

  2. Energy as a constraint

    Joule cost of a completed inference is a specified property

  3. Defined failure

    Incomplete work yields an explicit abort with a reason

  4. Fleet policy on ingest

    Approved firmware and model pairs enforced at every device

Advanced package
Advanced package
DESIGN TARGETS

Specification

Pre-silicon. Architecture specified; RTL in progress; FPGA next. Figures are design targets, not measured silicon results.

Attested Infrastructure Inference design targets
Status Architecture defined; public whitepaper
Design centre Verifiable completed inference under energy constraint
Contrast Datacentre optimises tokens/s/W
Output Result plus attestation bundle
Verification Operator check before workflow admission
Where it fits
  • Fleet policy enforcement
  • Billing admission
  • Protection decisions
  • Audit reconstruction
  • Approved-config gates
Engage

Talk to the design team

The specification is still open to review.

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