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DESIGN SERVICES

Silicon design work, taken on as engineering

Customers engage Nelix to design, prototype and validate custom hardware. That commercial work generates revenue that supports the long-term product roadmap. The same engineers specifying Nelix platforms take on external design work, from a contained block through to subsystem ownership.

Scoped to your programme gates: a two-week architecture review, or ownership of a subsystem through to sign-off.

Services active Platform pre-silicon
Entry point
Block or subsystem
Scope
Written in discovery
Handover
Documented for your team
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Advanced semiconductor package

Advanced package

Talent development pipeline

  1. University

    Cohort intake and coursework

    Active

  2. Mentorship

    Paired design review

    Active

  3. FPGA

    Prototyping and bring-up

    Active

  4. Verification

    Testbench and coverage closure

    Planned

  5. Product

    Tape-out readiness

    Planned

Engineers train on live design work, supervised by the engineers doing it.

University programme through to product · design intent
ENGAGEMENT

The engineers specifying the Nelix platform are the engineers on your programme.

Design work and the university programme fund the silicon effort and are what the team does today, with scope written down in a short paid discovery phase so the commercial terms follow the technical scope rather than the other way round.

  1. Scope

    A short paid discovery phase produces a written scope, a schedule and an explicit statement of what is not included.

  2. Execute

    Work runs against agreed milestones with your team in the loop. Source and documentation are delivered continuously, not at the end.

  3. Review

    Each milestone closes with a technical review. Findings and open risks are recorded rather than absorbed.

  4. Hand over

    Delivery includes the documentation and environment needed for your team to maintain the work without us.

CAPABILITIES

Scoped from the deliverable, not the label

Eleven capabilities in one directory. Each card names the design-flow stage it serves and the deliverables that leave the engagement.

Silicon design flow
  1. Feasibility
  2. Requirements
  3. Architecture
  4. RTL
  5. Verification
  6. Bring-up

Physical implementation stays in your flow. Design reviews attach at any gate.

  1. Architecture

    System Architecture

    Turning a product requirement into a defensible hardware specification.

    • Architecture specification
    • Partitioning trade study
    • Power and thermal budget
    • Interface definition
  2. RTL

    ASIC Design

    Digital design from specification through to tape-out support.

    • Micro-architecture specification
    • Synthesisable RTL
    • Timing constraints
    • Synthesis and STA closure support
  3. Bring-up

    FPGA Design

    Prototyping, bring-up and production FPGA loads.

    • FPGA implementation
    • Board bring-up
    • Debug and trace infrastructure
    • Characterisation results
  4. RTL

    RTL Development

    Synthesisable Verilog and SystemVerilog written to be reviewed.

    • Synthesisable RTL
    • Lint and CDC clean
    • Block documentation
    • Integration support
  5. Verification

    Verification

    Constrained-random and formal verification with measurable closure.

    • Verification plan
    • UVM environment
    • Coverage model
    • Formal properties
    • Closure report
  6. Architecture

    Security Architecture

    Threat modelling and root-of-trust design for devices that ship into hostile environments.

    • Threat model
    • Root-of-trust architecture
    • Key management and provisioning plan
    • Tamper response specification
  7. Bring-up

    Embedded Systems

    Firmware and drivers for the hardware underneath them.

    • Firmware
    • Device drivers
    • Bootloader and update path
    • Board support package
  8. Architecture

    AI Hardware

    Accelerator and dataflow design for constrained power budgets.

    • Quantisation analysis
    • Dataflow architecture
    • Accelerator micro-architecture
    • Energy per inference model
  9. Any gate

    Design Reviews

    Independent technical review at programme gates.

    • Findings report ranked by risk
    • Review session with the team
    • Remediation recommendations
  10. Requirements

    Product Requirements

    Turning field conditions into requirements an engineer can build against.

    • Requirements specification
    • Environmental and compliance constraints
    • Acceptance criteria
  11. Feasibility

    Semiconductor Consulting

    Feasibility, technology selection and cost modelling before you commit.

    • Feasibility assessment
    • Technology and IP selection
    • NRE and unit cost model
    • Vendor evaluation
RATIONALE

Why this team

Illustrative system architecture engineering context

Engineering environment

Design experience, not resale

The team is implementing a trusted compute architecture of its own. The services engagement is the same engineering practice, not a separate consulting arm.

Illustrative FPGA and RTL engineering context

Engineering environment

Security is not an add-on

Root of trust, attestation and tamper response are core to our own roadmap, so they can be designed into your part from the start.

Illustrative hardware bring-up context

Engineering environment

Built for difficult deployments

Our design assumptions come from infrastructure that runs on unreliable supply and narrow bandwidth, which travels well to any demanding environment.

Which gate are you working towards?

Tell us the gate and what is blocking it. An engineer replies.

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