For Developers

Build on sovereign & trusted silicon

RTL, FPGA reference designs, and SDKs for Nelix AI accelerators and security SoCs. Pre-silicon today, taping out 2027 — early access opens for design partners ahead of first silicon.

01 — Developer Tools

What you can use today & what's coming

Nelix is pre-silicon, with first tape-outs scheduled for 2027 (InferEdge™ on Intel 16, SecureGrid™ NL-100 on 55nm). Until then, our developer experience runs on FPGA reference designs and bring-up tooling. Design partners get early access ahead of public release.

[ FPGA REFERENCE ]

InferEdge™ FPGA Reference

RTL, bitstream, and constraints for the InferEdge™ systolic array, targeting AMD Spartan-7 (XC7S50). Bring-up guide and synthesis scripts included. Works with Vivado and the open-source Yosys / OSS CAD Suite flow.

Early Access Q4 2027

[ AI SDK ]

InferEdge™ Software Stack

Two-tier SDK: a high-level PyTorch / ONNX front-end with INT8 quantization, and a low-level C/C++ runtime for direct kernel control. Open source at first silicon.

Early Access Q4 2027

[ SECURITY IP ]

SecureGrid™ Security IP & SDK

PUF-based root of trust, AES-256 / SHA-2 / ECC engines, and HMAC-DRBG conditioning. Targeting NIST SP 800-90A / 90B compliance, NIST CAVP validation, and PSA Certified Level 2 RoT Component evaluation.

Early Access Q4 2027

[ CLOUD SANDBOX ]

Cloud Evaluation Sandbox

Remote access to a hosted Nelix FPGA cluster — run inference, profile workloads, and compile against the InferEdge™ toolchain without local hardware. Roadmap item for design partners.

Roadmap 2027

[ DOCS ]

Technical Documentation

Architecture specs, ISA reference, app notes, and worked examples for both InferEdge™ and SecureGrid™. Written by the engineers designing the silicon. Released on a rolling basis to design partners.

Rolling Release

[ PARTNERS ]

Design Partner Program

Direct access to Nelix engineers for architecture reviews, integration support, and shaping the spec. Partners get first access to RTL, FPGA bitstreams, and pre-silicon SDK builds. Apply for the 2026 cohort.

Applications Open

02 — Code Sample

Edge AI inference, illustrative API

An illustrative example of the planned InferEdge™ runtime API — model load, INT8 input, and on-chip inference. Final API will ship with the SDK at first silicon; this sample shows the intended developer experience.

inferedge_hello.c (illustrative)

// Illustrative: planned InferEdge™ runtime API #include "inferedge.h" #include "nelix_io.h" int main(void) { // Initialize the accelerator and load a quantized model inferedge_init(); ie_model_t *model = inferedge_load_model("mobilenet_v2_int8.nlx"); // Capture a frame and wrap it as an INT8 input tensor uint8_t frame[224 * 224 * 3]; nelix_camera_capture(frame, sizeof(frame)); ie_tensor_t input = ie_tensor_from_u8(frame, (ie_shape_t){1, 224, 224, 3}); ie_tensor_t output = ie_tensor_alloc((ie_shape_t){1, 1000}); // Run inference on-chip — no cloud, no round-trip if (inferedge_infer(model, &input, &output) == IE_OK) { int top_class = ie_tensor_argmax(&output); printf("Prediction: class %d\n", top_class); } inferedge_free_model(model); return 0; }

Apply to the Design Partner Program

We work directly with a small group of OEMs, system integrators, utilities, and research labs ahead of first silicon. Partners help shape the spec, get early RTL and FPGA bitstreams, and influence the SDK roadmap.

Apply for Partnership → View Technology

2026 cohort applications open. Limited slots — we work closely with each partner.