From dev kit to deployed fleet
Toolchains, APIs, and evaluation platforms for building on Nelix silicon. We are pre-silicon today — evaluation runs on FPGA platforms, and design partners work directly with the engineers writing the RTL. Everything below is built for the same end state: code you write on a dev kit runs unchanged on a fleet you can attest.
Three stacks, one AII foundation
Attested Infrastructure Inference runs on three developer surfaces — infrastructure firmware, JBIA inference, and the TrustCore Trust Continuum — unified on the Nelix Compute Platform so trust established at boot follows your code from dev kit to fleet.
SecureGrid™ SDK
Firmware toolchain for the S-Series infrastructure SoC — C runtime, metering reference stacks, and tamper-aware telemetry on TrustCore-secured silicon.
InferEdge™ SDK
JBIA completion transactions on InferEdge™ NPUs — ONNX in, INT8/INT4 quantized workloads under Energy Contract, with ICSM-managed rollouts and PCI export for attestation-backed inference results.
TrustCore™ APIs
The TrustCore Trust Continuum from manufacture through fleet lifecycle — PUF-derived identity, continuous attestation, and signed OTA on every Nelix die.
Quantize. Flash. Attest.
The Attested Infrastructure Inference path, end to end: compile ONNX through the JBIA pipeline to INT8/INT4 under Energy Contract, stage via ICSM-managed deploy, and verify TrustCore attestation before fleet admit. No attestation — no trusted admit. Today this runs on InferEdge™ FPGA evaluation targets.
- One CLI — JBIA compile, ICSM checkpoint, and TrustCore attest across the Nelix Compute Platform.
- PCI export — quantized workloads ship as Proof-Carrying Inference bundles, verified before execution.
- No attest → no admit — continuous Trust Continuum attestation gates fleet join; offline queues until reconnect.
FPGA evaluation today, silicon dev kits on the roadmap
We are honest about where we are: Nelix has not yet taped out. Evaluation runs on FPGA platforms that implement the SecureGrid and InferEdge RTL at reduced clock — enough to exercise the full Attested Infrastructure Inference path before silicon exists: JBIA inference, ICSM-managed rollouts, PCI export, and the TrustCore Trust Continuum. Silicon development kits follow first silicon on the roadmap.
FPGA access is offered to design partners under NDA — bitstreams, constraints, bring-up documentation, and direct support from the engineers writing the RTL.
Request Access| Platform | FPGA implementation of S-Series & EA-Series RTL |
| What you validate | JBIA pipelines, ICSM completion, PCI export, attestation bundles |
| Tooling | Same CLI and SDKs that will target silicon |
| Security | TrustCore Trust Continuum — boot and attestation paths |
| Access | Design partners, under NDA |
| Silicon dev kits | Planned · follow first silicon |
Platform docs for attested inference
Attested Infrastructure Inference documentation for design partners on the Nelix Compute Platform — architecture, TrustCore security, and Proof-Carrying Fleet Operations integration. Released on a rolling basis as the platform stabilizes; a public portal follows first silicon. Request documents under NDA until then.
Architecture Guides
InferEdge™ JBIA and SecureGrid™ block architecture — ICSM deploy model, Energy Contract limits, and sub-15 W power envelopes.
Request Under NDASecurity Model
TrustCore Trust Continuum from manufacture to fleet — attestation bundles, PCI export boundaries, and no attestation, no trusted admit.
Request Under NDAIntegration References
Proof-Carrying Fleet Operations — PCI and API integration for SCADA, cloud, and metering head-ends.
Browse ResourcesBuild with us before first silicon
Design partners get early access to FPGA platforms, SDK preview builds, and the engineers behind the architecture — and help shape the specification before tape-out.