Path to first silicon
Building a fabless semiconductor company is a sequence of hard, verifiable milestones. This is ours — stated plainly, with the current status of each stage. No stage is marked complete until it is.
Development timeline
Architecture & Specification
Instruction set, memory architecture, security model, and power envelopes defined for both product families, with the TrustCore root of trust specified as the common security foundation across every die.
RTL Design & Verification
Writing and verifying the register-transfer-level design: the SecureGrid secure MCU subsystem, the InferEdge systolic array and runtime control, and the TrustCore boot and attestation logic — under a growing regression and formal verification suite.
FPGA Validation
Running the architectures on FPGA platforms to validate firmware, model pipelines, and security flows at system level — the same platforms design partners use for evaluation today. Findings feed directly back into RTL before tape-out.
Test Chip / MPW Tape-Out
First trip to the foundry: critical blocks — the PUF, crypto engines, and systolic array tiles — fabricated on a multi-project wafer to de-risk the physical design before committing to full product tape-outs.
First Silicon Bring-Up
Packaged parts on the bench: power-on, boot, PUF characterization across temperature and voltage, security validation, and correlation of silicon behaviour against FPGA and simulation results. Silicon dev kits for partners follow from this stage.
Pilot Deployments
Silicon in the field with partner utilities and OEMs: metering endpoints and edge AI nodes running under real grid conditions, managed through the Nelix Compute Platform with fleet attestation and signed over-the-air updates.
Back the path, or build on it
Investors and partners who engage before first silicon shape the specification and stand first in line when it ships. Talk to us about where you fit on this timeline.