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CAPACITY BUILDING

Hardware engineering capacity, built on live work

Universities, curriculum, internships and FPGA/RTL training that build hardware engineering capacity in Africa.

Programme active Agreed per institution
Placements
Named supervising engineer
Scope
Finishable inside the placement
IP terms
Agreed before the work
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Illustrative design review workstation

Supervision at the workstation

Talent development pipeline

  1. University

    Cohort intake and coursework

    Active

  2. Mentorship

    Paired design review

    Active

  3. FPGA

    Prototyping and bring-up

    Active

  4. Verification

    Testbench and coverage closure

    Planned

  5. Product

    Tape-out readiness

    Planned

Engineers train on live design work, supervised by the engineers doing it.

FPGA first · the teaching platform and the validation route
POSITION

Part of the business, not outreach.

Experienced RTL and verification talent is scarce locally. The programme develops it on real blocks, with supervision from engineers doing the same work.

Illustrative field infrastructure context
Source of tasks is the live roadmap
STRUCTURE

The programme, end to end

Curriculum through supervised placement to a defined research-to-roadmap path.

  1. University Partnerships

    Joint work with engineering faculties on curriculum and research.

  2. Internships

    Supervised placements on live design work.

  3. Semiconductor Curriculum

    Course material built around the flows engineers actually use.

  4. FPGA Training

    From HDL fundamentals to board bring-up.

  5. ASIC Design Training

    Synthesis, timing and physical awareness.

  6. Mentorship

    Engineer-to-engineer supervision, not a lecture series.

  7. Research Collaboration

    Co-supervised research on trusted and energy-bounded compute.

  8. Commercialisation Pathway

    A defined route from research result to product decision.

Illustrative long-life field equipment
Capability that stays local
OUTCOMES

What each side gets

Stated separately, because the programme only works if it is worth running for everyone in it.

  1. For students

    Design experience on real hardware problems, reviewed by working engineers, plus a portfolio that stands up to technical interview.

  2. For departments

    Curriculum input and project supervision from an active design team, and research topics with an industrial counterpart.

  3. For Nelix

    A recruitment pipeline of engineers already familiar with our tools, review standards and design conventions.

ENGAGE

Who we want to hear from

Departments, students and funders start in the same place

Tell us which you are and what you want to build.

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