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ABOUT NELIX

Attested Infrastructure Inference for systems that cannot depend on the cloud

Nelix Chip Design Ltd. is a fabless semiconductor company headquartered in Accra, Ghana. We engineer InferEdge JBIA accelerators, TrustCore-secured processors, and SecureGrid infrastructure silicon that deliver Proof-Carrying Inference — completion transactions with cryptographic proof — for power-constrained, connectivity-limited, and mission-critical deployment.

Pre-silicon RTL in progress Fabless design house
Advanced semiconductor package

Advanced package

Boundary Attestation
Attestation boundary between device and operator A conceptual diagram of the attestation boundary. On the left, inside the device domain, a measurement store, a nonce buffer and a key handle feed a quote generator that binds measurements to a fresh challenge and signs the result. A hatched membrane with a single aperture separates the device from the operator domain on the right, where a verifier checks the quote against a trust anchor and a policy store before issuing an admit or deny decision. Only the challenge and the signed quote pass through the aperture. Device domain Operator domain Attestation boundary One aperture · signed payloads only Measurements Digest chain Nonce Freshness Key handle Attest key Quote Bind & sign Digests Nonce Device id Signed per challenge Verifier Check chain Anchor Root cert Policy Admit rules Decision Admit / deny Signed quote Challenge nonce Inside Outside
  • Signed quote outward
  • Challenge inward
  • Everything else stops at the band
The operator never reaches inside the device: it sends a challenge and checks the signature that comes back.
Attestation boundary · design intent
01 — OUR MISSION

Attested Infrastructure Inference, <span>engineered in Accra</span>

We specify compute where identity, measured boot and attestation sit on the execution path. The operator verifies the evidence; the device never asserts its own trustworthiness.

WHAT WE ARE BUILDING

One trust path, from die identity to fleet admission

Every layer is specified against the same attestation boundary.

  1. Die identity

    A root of trust that can be named and checked.

  2. Measured boot

    Evidence collected on the execution path, not asserted by the device.

  3. Attestation

    Signed payloads an operator can verify independently.

  4. Fleet admission

    Only work whose evidence matches is admitted.

Illustrative field hardware context
02 — OUR STORY

From FPGA validation to <span>first silicon</span>

How the architecture works

Nelix began with a field observation: critical infrastructure AI is moving to the edge, but most inference still runs on general-purpose compute or imported accelerators never designed for unstable power, high ambient heat, or networks that spend part of their life offline.

Our founding team set out to build Attested Infrastructure Inference in Accra — a shared TrustCore trust plane, InferEdge JBIA completion transactions, SecureGrid measurement integrity, and Proof-Carrying Inference export before any model executes.

Today our platform runs on FPGA validation platforms while we work with foundry and ecosystem partners toward first tape-out. We publish progress honestly — we are pre-silicon, and we intend to earn trust the way attestation does: by being verified.

TEAM

The people building it

Names and roles from the company roster. Photos and the full leadership page live under Leadership — this band stays a directory, not a second hero.

  • Dr. Michael Ayiania Founder & CEO
  • Dr. Felix Njeh President & CSO
  • Harshil Patel Head of Business Development (Strategic Role)
  • Isaac Danso IC Design Engineer
WHERE WE ACTUALLY ARE

Nothing has been fabricated yet

There is no Nelix part in the field and no benchmark to quote. The commercial activity today is semiconductor design services and engineering training, which is what funds the silicon programme.

Programme stage

  1. Architecture

    Defined for the research gap and the trust path.

  2. RTL

    In progress. Blocks under review, not frozen.

  3. FPGA validation

    Next. Programmable bring-up before any mask set.

  4. First silicon

    Not before 2029. No fabricated Nelix part exists today.

Facts on record

Silicon fabricated
None
Shipping product
None
Revenue today
Design services and training
Validation route
FPGA before ASIC
First silicon
Not before 2029
ENGAGE

Build this with us

The specification can still change. That stops being true after tape-out.